Analog-to-digital converters (“ADCs”) are an important means of providing inputs from a largely analog natural world to today's largely digital computing environment. One problem with ADC technology is that an ADC necessarily divides an analog input signal into discrete levels or steps capable of being interpreted by a binary computing system. Analog signal magnitude variations which occur between minimum step levels are not captured by the ADC. And, error components result if the ADC generates unequal digital output steps. Consequently, the digital translation of the analog input signal is, generally speaking, inexact.
Technology advances have created a need to translate analog inputs with increasingly finer resolutions. Various ADC circuit architectures such as subranging/pipelined, successive approximation, flash and sigma-delta have been developed to provide resolution/bandwidth trade-offs appropriate to various applications. The sigma-delta ADC can provide very high resolution of relatively low bandwidth signals such as are found in speech applications or even the conversion of near direct current (“DC”) telemetry signals.
FIG. 1 is a prior-art block diagram of a sigma-delta ADC 100 including a single-level sigma-delta modulator 105 The modulator 105 oversamples an analog signal appearing at a modulator input terminal 110 at a rate f_s 112. The modulator 105 generates a pulse density modulated pulse stream at an output terminal 115. The ratio of a count of a number of pulses (i.e., a count of a number of binary logical 1's) in the pulse stream divided by a total number of samples clocked during a known interval represents the instantaneous magnitude of the analog signal at the input terminal 110 during the interval. Individual samples of any given point of the input waveform are accumulated over time and averaged by a decimator 120. The decimator 120 generates an ADC output word at a data rate f_d 125 at an output terminal 130.
The sigma-delta modulator 105 includes a comparator 135 which acts as a single-bit quantizer to convert the analog input signal to a one or zero level coarse output at each sampling time. As with any quantizer, the comparator 135 output includes a quantization error. The modulator 105 also includes a single-bit digital-to-analog converter (“DAC”) 140 as a negative feedback element. The DAC 140 responds to each transition of the comparator 135 by changing an analog output error signal at an output terminal 143 of a difference amplifier 145. The analog output error signal at the terminal 143 includes quantization noise. The feedback loop operates to drive the error signal to zero such that the output of the DAC 140 becomes equal to the modulator analog input signal at the input terminal 110.
An integrator 150 combined with the sampling strategy outlined above shapes the quantization noise by pushing the noise energy into higher frequency spectra, away from input signal frequencies. Thus, the sigma-delta ADC architecture reduces quantization noise relative to some other architectures.
FIG. 2 is a prior-art block diagram of a sigma-delta ADC 200 including an N-level sigma-delta modulator 205. The N-level modulator 205 encodes log2N binary output bits, typically on N one-hot coded bit output lines. The modulator 205 includes an N-level quantizer 210 rather than the 2-level comparator 135 of FIG. 1. At each sampling time the N-level quantizer 210 resolves the analog signal at its input to one of the N levels and sets the output line corresponding to the resolved level to a binary logical 1 state. The other N−1 output lines not corresponding to the resolved level are set to a binary logical 0 state. The modulator 205 also includes an N-level DAC feedback element 215 rather than the 1-bit, two output-level DAC feedback element 140 of FIG. 1.
The N-level sigma-delta modulator 205 is capable of operation at lower sampling frequencies than the two-level modulator 105 for a given resolution. Alternatively, the N-level modulator 205 provides higher resolution than the 2-level modulator 105 at a given sampling frequency. The dynamic range of the N-level modulator 205 is also greater that of the 2-level modulator 105.
The modulator 205 also includes an Mth order loop filter 220 rather than the first-order loop filter of the modulator 105 implemented as a single integrator 150. A higher order loop filter provides a steeper noise shaping, thus pushing more quantization noise into higher frequency bands, away from the desired signal band.
One source of sigma-delta N-level modulator output error components results from unequal analog output steps generated by the N-level feedback DAC. DAC output levels are typically generated using current sources made up of MOS transistors. In practice there is always mismatch between the different current sources due to mismatches in physical dimensions as well as process variations across a die.